1. Field of the Invention
The present invention relates to a row decoder for a semiconductor memory device, and more particularly, to a driver of a row decoder having an optimized layout.
2. Description of the Related Art
In semiconductor memory devices, a sense amplifier, a sub-wordline decoder, a column decoder, and a row decoder are laid out in accordance with a cell pitch of a memory array. The row decoder decodes a row address and selects a wordline of a memory cell for application of a voltage required for accessing a memory cell. Accordingly, the row decoder typically includes a decoder portion for decoding a row address and a driver portion for driving the required voltage on the selected wordline.
In the conventional layout of a driver of a row decoder (hereinafter, a row decoder driver), the width of the row decoder driver is an integer multiple of the cell pitch. The layout typically includes a PMOS driver and an NMOS driver associated with each wordline, and the sources/drains and channels of the PMOS and NMOS drivers have widths running in the direction of the wordline. With this layout, the cell pitch is generally insufficient to permit source contacts and drain contacts that face each other on opposite sides of a gate area. Accordingly, the source and drain contacts must be offset from each other in the wordline direction. As a result, the effective area of the driver is much smaller than the laid-out area the driver, and the driver takes longer to enable a wordline. This increases the critical Ras to Cas delay times tRCD and tRP in a synchronous DRAM and reduces the performance characteristics of the synchronous DRAM. Also, the row decoder driver is larger than necessary, so that a standby current and power consumption are correspondingly larger than necessary.